Re: [Rpcemu] Patch to abort model for ARM6/7

In article
<CAJjzs2A4NGeEV+fq+OmwegVZz-W1nNj8HYL742dsRAF3WNXRLQ@mail.gmail.com>,
Matthew Howkins <rpcemu-list@howkins.me.uk> wrote:
> > The emulation of memory accesses (LDR[B]/STR[B]/LDM/STM) in RPCEmu
> > currently mostly follows the base restored model, ie. StrongARM
> > or ARM810 class.
>
> Thanks for this patch.
>
> I'm currently spending a lot of time developing test code, and intend to
> use it to both discover deficiencies in the emulation and to verify any
> patches.
>
> It will probably be a few days before I'm in a position to fully test and
> then commit your code; I'm keen to make sure that my testing keeps up with
> any improvements to the ARM core.

Hopefully you new test code will shake out what the subtle difference
between the interpreter and recompiler is now, I took a quick look at the
code generator but I'm not familiar enough with x86 assembler to see
anything obvious.

If you're writing tests, I'm sure someone somewhere will have done something
horrible like

STMIA r5!, {r4-r6}

strictly speaking the above stores an unknown value for r5 according to the
ARM ARM since it's not the first register in the list, but I'm sure it would
have been deterministic prior to ARMv5 it's just ARM aren't saying so!
Sprow.


_______________________________________________
Rpcemu mailing list
Rpcemu@riscos.info
http://www.riscos.info/cgi-bin/mailman/listinfo/rpcemu