Re: [gccsdk] Unaligned data access vs pack(push...

On Fri, Aug 24, 2012 at 01:03:05PM +1200, Ron wrote:
> The ARM_FEATURE_UNALIGNED reportedly will be on the latest gcc and
> can increase the compression speed by 50% on processors that support
> it (arm6 and higher I think)

I've just been writing the alignment exception configuration for Raspberry
Pi (ARMv6). Essentially there are 3 modes, on ARMv6 and ARMv7 controlled
by bit 22 (U) and bit 1 (A) of CP15 register C1.

Consider this code:
ADR r0,label
LDR r1,[r0,#2]
.label
DCD &01234567
DCD &89ABCDEF

1. ARMv2-5 or ARMv6 in rotated load emulation mode (A=0, U=0) return
r1=&45670123 This is not available on ARMv7.

2. ARMv6/ARMv7 with alignment exceptions on (A=1, U=don't care)
Cause an exception, instruction never completes

3. ARMv7 with alignment exceptions off (A=0), ARMv6 with exceptions off and
rotated loads off (A=0, U=1), return &456789AB

[I may have the endian-ness wrong on those]

If you want to use ARM_FEATURE_UNALIGNED, I assume you need to be in A=0,
U=1 mode for it to work. ie it will only work on ARMv6 and ARMv7 with
alignment exceptions off. BeagleBoard defaults to exceptions on.

So, unless you're willing to put in a test of A and U beforehand, your code
may break on new CPUs depending on how they are configured. The intention
is to ship a configure plugin with Raspberry Pi to set the mode, so you
can't assume what it will be.

For really critical things it may be worth including two copies of the key
functions, one with the option on and another with it off, but you'll have
to write something to switch at runtime yourself - it can't be a compiler
option. It could potentially be a switch between two shared libraries.

> I noticed a wiki on Endian with a list of OS's doesn't include
> RISC OS, perhaps someone knowledgible could add something there?

RISC OS is little endian, though that doesn't concern the above situation.
[Well, it does slightly; U=1 in the processor manual mentions something
about mixed endian support. I haven't looked at that]

> > One other config question is wether we support hardware bit counting,
> > in case that means something to anyone?

Well there's CLZ (count leading zeroes) in ARMv5 onwards, if that's what
they mean?

Theo

_______________________________________________
GCCSDK mailing list gcc@gccsdk.riscos.info
Bugzilla: http://www.riscos.info/bugzilla/index.cgi
List Info: http://www.riscos.info/mailman/listinfo/gcc
Main Page: http://www.riscos.info/index.php/GCCSDK