Tuesday, 11 August 2020

Re: [Rpcemu] Fix for crash on reset from within the emulator

In article
<CAJjzs2BDv1-txa95eMW6c-g1PZgeX5PEwDYeAuk=sa2UOfoM0Q@mail.gmail.com>,
Matthew Howkins <rpcemu-list@howkins.me.uk> wrote:
> On Sun, 9 Aug 2020 at 09:54, Sprow <webpages@sprow.co.uk> wrote:
> > When in the emulator (both Interpreter or Recompiler) if you choose
> > "Shutdown" from the task manager's menu, then click on "Restart" on the
> > resulting dialogue box on RISC OS 5 this causes emulator 0.9.3 to fatally
> > exit with
> >
> > Bad PC FC001000 FC001000
> >
> > Going back to 2006 in Mercurial there are vestiges of similar things, so
> > another approach would be to properly emulate the pipeline (ie. set
> > pccache = 0xffffffff after <pipeline depth> cycles have elapsed) but
> > if we assume RISC OS is sensible and does TLB maintenance when it
> > is truly required that would end up calling cp15_tlb_flush_all()
> > anyway, so CP15 register 1 can stick to just doing control type things.
>
> Thanks for this.
>
> The code in the emulator differs slightly from a real MMU because we cache
> some information that doesn't exist, or use caches slightly different from
> real hardware for performance reasons.
>
> I do recall that without those code changes there were versions of RISC OS
> which would not boot at all when combined with certain combinations of
> hardware settings (regarding CPU/VRAM).

I didn't try all possible combinations, just "lots of RAM" and "not much RAM"
for each, so it'd be interesting to know which versions failed to boot at all.

> The ideal fix for this would be to emulate the pipeline precisely, but that
> would come with significant overhead and few benefits. A workaround like
> your patch would seem to be a pragmatic approach.

Yeah - the effort of emulating the pipeline for the super specialist use case
of wanting to run the next 3 instructions when the underlying memory has been
mapped out felt a bit extreme.

I suppose another possibility would be to just not set pccache = -1 when the
control register is written, but do the other TLB side effects if that helps
some other ROM. It was only the pccache = -1 that was the real killer here,
Sprow.


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