Re: [Rpcemu] PATCH: Implement OS_Reset "0x0ff"

changeset: 1150:e1de572e7804
branch: trunk
user: rrt@sc3d.org
date: Mon Sep 10 23:23:00 2018 +0100
summary: Add support for powering off

diff -r f224afc8c4d6 -r e1de572e7804 src/arm_common.c
--- a/src/arm_common.c Mon Sep 10 23:22:01 2018 +0100
+++ b/src/arm_common.c Mon Sep 10 23:23:00 2018 +0100
@@ -38,6 +38,8 @@
#define SWI_OS_Byte 0x6
#define SWI_OS_Word 0x7
#define SWI_OS_Mouse 0x1c
+#define SWI_OS_ReadSysInfo 0x58
+#define SWI_OS_Reset 0x6a
#define SWI_OS_CallASWI 0x6f
#define SWI_OS_CallASWIR12 0x71

@@ -372,6 +374,19 @@
}
}

+ /* Intercept OS_Reset to check for turning off
+ https://www.riscosopen.org/wiki/documentation/show/OS_Reset
+ */
+ if (swinum == SWI_OS_Reset) {
+ if (arm.reg[0] == 0x46464F26) { /* "&OFF" */
+ exit(0);
+ }
+ } else if (swinum == SWI_OS_ReadSysInfo && arm.reg[0] == 8) {
+ arm.reg[0] = 0; /* Unknown hardware platform */
+ arm.reg[1] = 0x08; /* Software control over PSU supported */
+ return;
+ }
+
/* Intercept RISC OS Portable SWIs to enable RPCEmu to sleep when
RISC OS is idle */
if (config.cpu_idle) {

On Wed, 31 Oct 2018 at 11:49, Ralph Corderoy <ralph@inputplus.co.uk> wrote:

Hi Reuben,

Couple of minor comments.

> +     /* Intercept OS_Reset to check for turning off
> +        https://www.riscosopen.org/wiki/documentation/show/OS_Reset
> +     */
> +     if (swinum == SWI_OS_Reset) {
> +             if (arm.reg[0] == 0x46464F26) { /* 0x0ff */

It's "&0ff", not 0x0ff.

Thanks (corrected to "&OFF"; a case where the code lagged behind the comment). Indeed, the online documentation at https://www.riscosopen.org/wiki/documentation/show/OS_Reset has the right hex but the wrong ASCII.

 

Use `else if' as the previous if being true might not result in the
exit().

Fixed. Arguably the whole opSWI function would benefit from switching on swinum and only then applying other conditions; the logic is a little tortuous at the moment.

New version attached.

--

https://rrt.sc3d.org